Digital ASIC Design Engineer (m/f/x)

Your Responsibilities:

• Developing digital ASIC/SoC components from specification through RTL design and verification to handoff to synthesis and physical implementation.
• Implementation of digital functions in Verilog and SystemVerilog, taking into account performance, chip area, power consumption, latency, and timing.
• Developing data paths, control logic, state machines, registers, memories, interfaces, and digital subsystems.
• Translating system and block requirements into clearly structured, robust, and verifiable RTL architectures.
• Creation and maintenance of design specifications, register definitions, and interface and integration documentation.
• Defining and coordinating interfaces between digital blocks as well as with analog, RF, and firmware components.
• Supporting the integration of digital blocks into complex SoC and mixed-signal environments.
• Close collaboration with SoC Architecture, Design Verification, Synthesis & Physical Implementation, Firmware, System Engineering, and Analog/RF Design.
• Analysis and resolution of design, integration, timing, and verification issues across teams and domains.
• Support for linting, clock-domain crossing, reset-domain crossing, and formal checks.
• Support for synthesis, as well as the preparation and handoff of RTL, constraints, and technical documents to Synthesis & Physical Implementation.
• Supporting the development process from architecture and RTL implementation through tape-out, silicon bring-up, and product release.
• Creation and maintenance of design, integration, and verification documentation.
• Early identification of technical risks, as well as coordination and implementation of appropriate countermeasures.
• Contributing to the further development of design methods, coding guidelines, review practices, and development processes in a growing deep-tech company.

Your Profile:

• A bachelor’s or master’s degree in electrical engineering, microelectronics, telecommunications engineering, computer science, computer engineering, or a comparable qualification.
• Several years of practical experience in digital design for ASICs, SoCs, FPGAs, or comparable complex embedded systems; typically, you have at least five years of relevant professional experience outside of your studies and internships.
• Solid practical experience in RTL design using Verilog and/or SystemVerilog.
• A solid understanding of digital circuit design, synchronous logic, finite-state machines, data paths, registers, memory, and digital interfaces.
• Experience with timing, clocking, reset strategies, and the fundamental requirements for synthesis and physical implementation.
• You can translate technical requirements into clearly structured, robust, and verifiable RTL implementations.
• Experience with digital interfaces, register definitions, and the integration of hardware/software interfaces.
• Ability to evaluate design decisions regarding performance, area, power consumption, timing, complexity, and robustness.
• Experience analyzing and resolving RTL, integration, timing, and verification issues.
• A structured, analytical, and solution-oriented approach to work, as well as a high degree of personal responsibility.
• Good written and spoken English skills for working in an international team.

Nice-to-have:

• Experience with
  • complex SoC/ASIC designs, particularly those with multiple clock domains and mixed-signal or RF interfaces.
  • DECT NR+, DECT-2020, 4G/5G, Wi-Fi, Bluetooth, or comparable communication systems.
  • EDA tools for RTL simulation, linting, CDC/RDC analysis, synthesis, and timing analysis.
  • Tcl, Python, Perl, or comparable scripting languages for automating design and analysis workflows.
  • Low-power design, clock gating, power intent, or UPF.
  • FPGA prototyping, emulation, ASIC tape-out, or silicon bring-up.
  • DFT, scan, ATPG, or manufacturing test requirements.
• Knowledge of SystemVerilog, assertions, simulation-based verification, formal verification, or UVM. Good knowledge of hardware/software interfaces, register maps, firmware requirements, and driver concepts.
• Experience with safety-critical, reliability-critical, or highly energy-efficient embedded systems.
• Experience in establishing and refining coding guidelines, design reviews, and reproducible development processes.
• Experience in a startup or scale-up environment, as well as a passion for pragmatic decision-making and short development cycles.

We offer:

Creative freedom & responsibility

• Ample creative freedom and genuine ownership instead of micromanagement
• Short decision-making paths and direct influence on strategic decisions
• A tangible contribution to the success of our product and company
• The opportunity to play a key role in a growing deep-tech company
• Contributing to a technology that can transform the future of wireless communication

Benefits

• Employer contribution toward the Deutschlandticket or DVB Jobticket in the amount of €55.10 per month
• Alternatively, an employer contribution toward the JobRad of €54.90 per month
• Unlimited free gym access right in the building
• Retirement savings and disability insurance with employer contributions ranging from €100 to €200 per month

Flexibility & Work Environment

• Flexible work hours with core hours from 10:00 a.m. to 3:00 p.m.
• Hybrid work with a high degree of flexibility
• Modern hardware and professional work equipment
• Bright, modern office spaces in a central location in Dresden
• Ergonomically designed workstations

Team & Culture

• An international team with flat hierarchies and short lines of communication
• Direct interaction with management and technical decision-makers
• Colleagues who support one another and share knowledge
• Lunch breaks together and regular team events
• A corporate culture in which initiative and new ideas are actively encouraged